This invention relates generally to computer graphics, and more specifically to techniques for reducing time spent clearing areas of the frame buffer.
In computer graphics, the operation of clearing a large area of frame buffer memory is very expensive in terms of both time and processing resources. For example, in a system having 1280xc3x971024 resolution, clearing the frame buffer requires accessing more than one million pixels. Indeed, clearing such a large area of memory can require more time than it takes to draw a frame of an image after the clear has been completed. Designers have attempted to address this problem either by speeding up the process of clearing or by avoiding the process altogether.
For example, frame buffers have been implemented using physical memory devices that have a special hardware clear feature. In such embodiments, the operation of clearing frame buffer memory is accelerated. On the other hand, such special-purpose physical memory devices add to the cost of the implementation.
Another technique is taught in U.S. Pat. No. 5,851,447, issued to Michael D. Drews and assigned to Evans and Sutherland Computer Corporation (hereinafter xe2x80x9cDrewsxe2x80x9d). Drews teaches allocating an additional field in frame buffer memory for each pixel and storing a version number in the additional field. An alternate pixel value (a clear value) and a current version number are maintained in a pixel processor. During frame buffer reads executed by the pixel processor, the version number corresponding to a pixel is read from the frame buffer first. If the version number read from the frame buffer is not equal to the current version number stored in the pixel processor, then the alternate pixel value stored in the pixel processor is substituted for the pixel value that would have been read from the frame buffer. On the other hand, if the version numbers are equal, then the pixel value is read from the frame buffer and used. According to this technique, multiple pixels in the frame buffer can be made to appear to have been modified simply by changing the current version number stored in the pixel processor. Thus, the frequency with which xe2x80x9crealxe2x80x9d clearing operations must be performed can be reduced.
One problem with the Drews technique is that it requires more storage space in the frame buffer for every pixel. This requirement represents a significant drawback in high-resolution systems wherein adding even a single byte of storage space to the frame buffer for each pixel can mean adding more than one million bytes of memory. Moreover, these newly-added bytes must be written every time a xe2x80x9crealxe2x80x9d clearing operation is performed, thus compounding the original problem.
Another problem with the Drews technique is that in many cases it prescribes more than one read for accessing pixel data from the frame buffer. This requirement represents a drawback as well, because read bandwidth must be preserved if frame buffer accesses are to be efficient.
Another problem with the Drews technique is that modem window-based computing environments allow multiple windows to be displayed on the screen at the same time. The Drews patent makes no mention of window-based computing environments, and it fails to teach or suggest how the Drews technique could be applied in such an environment. Indeed, the Drews patent appears to be concerned solely with activity within the pixel processor, to the exclusion of activity within the display controller.
It is therefore an object of the invention to provide a fast clear technique that is more efficient than Drews in terms of frame buffer memory and read bandwidth utilization.
It is a further object of the invention to provide a fast clear technique that is useful in a modern window-based environment in which more than one window may be displayed on the screen at the same time.
The invention includes numerous aspects, each of which contributes to the achievement of the above objects.
In one aspect, the invention includes a method and apparatus for organizing and utilizing an image buffer to reduce the frequency of buffer clear operations. A clear color value is stored in a first clear color register in a frame buffer controller and w also in a second clear color register in a video controller. A count value is stored in a first clear count register in the frame buffer controller and in a second clear count register in the video controller. The image buffer is cleared by writing the clear color value into a color bit field and writing the count value into a count bit field of each pixel. Thereafter, each time a frame is drawn into the image buffer, the count bit field of each pixel modified is updated with the count value stored in the first clear count register. After each frame, the count value in the first and second clear count registers is incremented. When the count value reaches a maximum, the process begins again with a clearing of the image buffer as described above.
In one embodiment, the color bit field and the count bit field are part of the same word of frame buffer memory. In another embodiment, the count value is stored in an alpha bit field of each pixel in the image buffer, in lieu of an alpha transparency value. A default alpha value is stored in a default alpha register in the frame buffer controller and, each time a pixel is read from the image buffer, the count value read from the pixel""s count bit field is replaced with the default alpha value. In this manner, frame buffer memory is saved by replacing the destination alpha value with the count value, and yet blending modes involving destination alpha may still be used with the default alpha value. In both of these embodiments, frame buffer memory and read bandwidth are conserved.
Each time a pixel is read from the image buffer by the frame buffer controller, the count value read from the pixel""s count bit field is compared with the count value stored in the first clear count register. If the two count values are unequal, the color value read from the pixel""s color bit field is replaced with the clear color value stored in the first clear color register. Also, whenever a pixel is read from the image buffer by the video controller, the count value read from the pixel""s count bit field is compared with the count value stored in the second clear count register. If the two count values are unequal, the color value read from the pixel""s color bit field is replaced with the clear color value stored in the second clear color register.
In a further embodiment, numerous sets of clear count, clear color, and clear enable registers are provided in the video controller. Each set corresponds to one window on the display. For each pixel read from the image buffer by the video controller, attribute bits corresponding to the pixel select one set of clear color, clear count, and clear enable registers to be used in the comparison and conditional color replacement steps. In this manner, the fast clear technique of the invention may be applied in environments in which more than one window is displayed at the same time.
In yet a further embodiment, numerous pairs of clear count and clear color registers are provided in the frame buffer controller to better support double buffering and stereo operations. Each pair of registers corresponds either to a front-left, front-right, back-left or back-right image buffer. A buffer count indicator (or another suitable indicator derived, for example, from a frame buffer address) may be used to select the appropriate pair of clear count and clear color registers for a given operation.